1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a construction of a semiconductor memory device having a redundancy construction.
2. Description of the Background Art
From the past days, in semiconductor memory devices, it is essential to add a redundancy circuit for improvement in the yield.
An example of such a redundancy circuit construction is xe2x80x9cdeficient bit relieving circuit in a semiconductor memory devicexe2x80x9d (Japanese Patent Application No. 2837433: Document 1). In this deficient bit relieving circuit, signals on and after the row or column line that is connected to a deficient memory cell are shifted to an adjacent row or column line thereby to exclude the deficient memory cell.
FIG. 9 shows a construction of the deficient bit relieving circuit shown in Document 1. Referring to FIG. 9, Cixe2x88x921 to Cj+3 represent columns; Yixe2x88x921 to Yj+3 represent column decoder output signal lines; QAixe2x88x921, QBixe2x88x921, QAi, QBi, QBjxe2x88x921, QAj, QBj, QAj+1, and QBj+1 represent switching elements; CB1 and CB2 represent common data lines, MC represents a memory cell, BL and /BL represent bit lines that are complementary with each other, and the reference numeral 9 represents a column selection gate.
The bit lines of the columns other than the column Cj+1 that is positioned at the boundary of Section I and Section II are each connected to either one of two common data lines via a column selection gate.
The bit line BL of the column Cj+1 is connected to the common data line CB1 via a transfer gate TG1 and is also connected to the common data line CB2 via a transfer gate TG2. The complementary bit line /BL of the column Cj+1 is connected to the common data line CB1 via a transfer gate TG1xe2x80x2 and is also connected to the common data line CB2 via a transfer gate TG2xe2x80x2.
The gate of each of the transfer gates TG1, TG1xe2x80x2 is connected to the column decoder output signal line Yj via the switching element QBj. The gate of each of the transfer gates TG2, TG2xe2x80x2 is connected to the column decoder output signal line Yj+1 via the switching element QAj+1.
The switching elements QBj and QAj+1 satisfy a relation such that, if one is in a conducted state, the other is a non-conducted state.
Even if a column Ci becomes deficient and the column decoder output signal line Yj is connected to the column Cj+1, the column Cj+1 is connected to Section I by the transfer gates TG1 and TG1xe2x80x2.
However, if the pertinent deficient bit relieving circuit is adopted for relieving a column line of the semiconductor memory device, the column lines must be shifted, thereby necessitating a complex construction at the boundary of the Sections (column groups).
In the meantime, a semiconductor memory device 9500 shown in FIG. 10 represents a redundancy construction in which the circuit construction at the boundary of the column groups is more simplified. Referring to FIG. 10, XM1 to XM3 represent memory blocks including a plurality of memory cells arranged in a matrix form, a plurality of column lines, and a plurality of row lines; 901 to 903 represent column selection circuits disposed respectively in correspondence with the memory blocks XM1 to XM3; 911 to 913 represent read/write circuits disposed respectively in correspondence with the column selection circuits 901 to 903; 920 represents a redundancy selection circuit; and DQ1 and DQ2 represent input/output data signals that are output from the redundancy selection circuit 920 or input into the redundancy selection circuit 920.
Each of the memory blocks XM1 to XM3 constitutes a column group. The column selection circuits 901 to 903 select one of the plurality of column lines in the corresponding memory block in accordance with the column selection signals Y1 to Yx. The read/write circuits 911 to 913 include circuits for reading data from or writing data into the memory cells via the corresponding column selection circuit. The read/write circuits 911 to 913 are activated in accordance with a read control signal SE or is activated in accordance with a write control signal WE.
The redundancy selection circuit 920 connects the node F1 with either one of the nodes E1 and E2 that are connected with the read/write circuits 911, 912, and connects the node F2 with either one of the nodes E2 and E2 that are connected with the read/write circuits 912, 913.
The redundancy selection circuit 920 shifts the connection relationship of the nodes F1 and F2 in accordance with the redundancy selection signals R1, R2. By shifting the connection relationship, two of the outputs of the read/write circuits 911 to 913 are transmitted to the nodes F1, F2.
Thus, in the semiconductor memory device 9500, a memory block including spare memory cells for one column group is prepared, whereby a column group (memory block XM2) including a deficient memory cell is excluded by selecting the outputs of the column groups.
However, such a construction of the semiconductor memory device 9500 necessitates redundancy memory cells for one column group although the construction at the boundary of the column groups is not complicated.
If the number of columns included in one column group is 16, redundancy memory cells for 16 columns are required. If the number of columns included in one column groups is 64, redundancy memory cells for 64 columns are required. Therefore, it raises a problem that, according as the number of columns included in one column group increases, the area efficiency decreases.
Thus, the present invention provides a semiconductor memory device having a redundancy construction with a good area efficiency with the use of a simple circuit construction.
A semiconductor memory device according to one aspect of the present invention includes a memory cell array including m memory blocks (m is an integer not smaller than 2) each having a plurality of memory cells arranged in a matrix form and n column lines (n is an integer) connected to the corresponding memory cells; m first selection circuits disposed respectively in correspondence with the m memory blocks, each of the m first selection circuits selecting one of the n column lines included in the corresponding one of the m memory blocks; m data processing circuits disposed respectively in correspondence with the m first selection circuits, each of the m data processing circuits including an amplification circuit for amplifying read data from the corresponding first selection circuit and a write circuit for outputting write data to the corresponding first selection circuit; a redundancy selection circuit that includes m first nodes and (mxe2x88x921) second nodes for respectively giving and receiving data to and from the m data processing circuits and selectively connects (mxe2x88x921) first nodes with the (mxe2x88x921) second nodes by shifting connections to exclude one of the m first nodes; and a second selection circuit that selects one of k second nodes (kxe2x89xa6mxe2x88x921: k is an integer) for giving and receiving data.
Preferably, (mxe2x88x921)/k amplification circuits are activated among the m amplification circuits at the time of reading data from the memory cell array. In particular, the amplification circuit is activated at the time of reading data from the corresponding memory block.
Preferably, (mxe2x88x921)/k write circuits are activated among the m write circuits at the timing of writing data to the memory cell array. In particular, the write circuit is activated at the time of writing data to the corresponding memory block.
A semiconductor memory device according to a further aspect of the present invention includes a memory cell array including m memory blocks (m is an integer not smaller than 2) each having a plurality of memory cells arranged in a matrix form and n column lines (n is an integer) connected to the corresponding memory cells; m first selection circuits disposed respectively in correspondence with the m memory blocks, each of the m first selection circuits selecting one of the n column lines including in the corresponding one of the m memory blocks; a redundancy selection circuit that includes m first nodes and (mxe2x88x921) second nodes for respectively giving and receiving data to and from the m first selection circuits and selectively connects (mxe2x88x921) first nodes with the (mxe2x88x921) second nodes by shifting connections to exclude one of the m first nodes; a second selection circuit that selects one of k second nodes (kxe2x89xa6mxe2x88x921: k is an integer) for giving and receiving data; and an amplification circuit for amplifying data output from the second selection circuit and a write circuit for outputting data to the second selection circuit.
Preferably, the second selection circuit includes a plurality of gates that are disposed respectively in correspondence with the k second nodes and are connected to the amplification circuit and the write circuit. In particular, the second selection circuit, the write circuit, and the amplification circuit are disposed in a plural number, and only write circuit for writing data to memory block that constitutes an object of writing data is operated among the write circuits disposed in the plural number.
Thus, according to the semiconductor memory device of the present invention, substitution with reduced area can be made with a simple circuit construction by including a read/write circuit, a redundancy selection circuit that selects an input/output node of the read/write circuit, and an input/output circuit that selectively connects the input/output node of the redundancy selection circuit with the data input/output line.
Further, according to the semiconductor memory device of the present invention, substitution with reduced area can be made with a simple circuit construction by including a column selection circuit, a redundancy selection circuit that selects an input/output node of the column selection circuit, and a selection circuit that selects the input/output node of the redundancy selection circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.